In recent years, as for liquid crystal display devices, a gate driver (scanning signal line drive circuit) for driving gate bus lines (scanning signal lines) have become increasingly monolithic. Conventionally, a gate driver has mostly been mounted as an IC (Integrated Circuit) chip on a peripheral part of a substrate that constitutes a liquid crystal panel. However, in recent years, it has gradually become more common to provide a gate driver directly on a substrate. Such a gate driver is called such as a “monolithic gate driver”. In a liquid crystal display device provided with a monolithic gate driver, a thin-film transistor using amorphous silicon (a-Si) (hereinafter referred to as an “a-SiTFT”) has been conventionally employed as a drive element. However, a thin-film transistor using microcrystalline silicon (μc-Si) or oxide semiconductor (e.g., IGZO) has become commonly employed in recent years. Mobility of microcrystalline silicon and oxide semiconductor is greater than that of amorphous silicon. Therefore, it is possible to achieve reduction of a picture-frame area and improved resolution by employing a thin-film transistor using microcrystalline silicon or oxide semiconductor as the drive element.
A display unit of an active matrix-type liquid crystal display device includes a plurality of source bus lines (video signal lines), a plurality of gate bus lines, and a plurality of pixel formation portions provided respectively corresponding to intersections between the plurality of source bus lines and the plurality of gate bus lines. These pixel formation portions are arranged in matrix to constitute a pixel array. Each pixel formation portion includes a thin-film transistor as a switching element having a gate terminal connected to a gate bus line that passes through the corresponding intersection and a source terminal connected to a source bus lines that passes through this intersection, a pixel capacitance for storing a pixel voltage value, and so on. Such an active matrix-type liquid crystal display device is also provided with the above-described gate driver, and a source driver (video signal line drive circuit) for driving the source bus lines.
Although video signals indicating pixel voltage values are transmitted through the source bus lines, the source bus lines cannot transmit video signals indicating pixel voltage values for more than one line at one time (simultaneously). Therefore, writing (charging) of the video signals to the pixel capacitances in the pixel formation portions arranged in matrix is performed sequentially line by line. Thus, the gate driver is configured by a shift register having a plurality of stages so that the plurality of gate bus lines are sequentially selected for a predetermined period. Each stage of the shift register constitutes a bistable circuit that takes one of two states (a first state and a second state) at one time point, and outputs a signal indicating this state (hereinafter referred to as a “state signal”) as a scanning signal. Then, the writing of the video signals to the pixel capacitances is sequentially performed line by line, as described above, based on sequential output of active scanning signals from a plurality of bistable circuits within the shift register.
In a conventional display device, the bistable circuit is configured as illustrated in FIG. 50 (FIG. 1 of Japanese Patent Application Laid-Open No. 2006-107692) or in FIG. 51 (FIG. 14 of Japanese Patent Application Laid-Open No. 2006-107692). In such a bistable circuit, when a scanning signal Gn-1 supplied from a previous stage is driven to a high level, a transistor group TG1 is turned to an ON state, and therefore a potential of a second-node N2 is turned to a low level. With this, transistors TG3 and TR4 are turned to an OFF state. Accordingly, by the scanning signal Gn-1 being driven to the high level, a potential of a first-node N1 is turned to the high level, and an output capacitor Cb is charged. In this state, a potential of a clock CK appears in the gate bus lines. As described above, by turning the potential of the clock CK given to each bistable circuit to the high level after the scanning signal Gn-1 supplied from the previous stage is driven to the high level in the each bistable circuit, active scanning signals are outputted sequentially from the plurality of bistable circuits within the shift register. With this, the plurality of gate bus lines are driven sequentially line by line. In each bistable circuit, the potential of the second-node N2 is maintained at the high level so that the potential of the first-node N1 is maintained at the low level during a period (a “normal operation period” that will be later described) other than a period in which the operation for outputting an active scanning signal is carried out.
Further, Japanese Patent Application Laid-Open No. 2001-52494, Japanese Patent Application Laid-Open No. 2003-16794, Japanese Patent Application Laid-Open No. 2005-94335, Japanese Patent Application Laid-Open No. 2006-106394, and Japanese Patent Application Laid-Open No. 2006-127630 also disclose a configuration of a shift register (bistable circuit) provided for a display device and such.